A memory controller includes a DDR memory interface circuit for DDR (Double Data Rate) 3 which is representative of DDR-based technology. DDR memory is a memory in which data is input and output on both positive and negative edges of a clock signal and transferred at a data transfer rate of twice the clock frequency.
In DDR memory technology, an internal clock signal generated within the memory controller is transmitted to a Dual In-line Memory Module (DIMM).
In addition, DIMM generates a data strobe DQS signal from the internal clock signal and sends the DQS signal together with a data DQ signal to the memory interface according to a read request from the memory controller.
The DQS signal and DQ signal are received at the memory interface side. Subsequently, the memory interface determines an optimum DQ signal capture timing based on phase information (edge) included in the received DQS signal. In addition, the memory controller captures the DQ signal at the determined timing.
The delay generated on a route along which the DQS signal or the DQ signal passes and on which, for example, a memory controller, a printed circuit board (PCB) or a memory element is located varies with the operational environment of a device such as, for example, a temperature or a power source voltage. Therefore, the timing at which the DQS signal and DQ signal arrive at the memory controller varies with the change of the operational environment of the device. Recently, as the data transfer rate is becoming increased, the influence of variation in delay is increasing.
There is a conventional technology in which the memory interface monitors the timing of DQS signal each time when a read operation is performed and adjusts the delay amount of a reception signal based on a result of the monitoring to cancel out the variation of the arrival timing in order to determine an optimum data capturing timing according to the variation in an arrival timing of signal. See, for example, International Publication No. WO2003/001732 and International Publication No. WO2011/077573.
However, as the speed of the memory interface has recently been increased as in the transition from DDR3 to DDR4, the timing margin for capturing the DQ signal using the DQS signal has been decreased. Further, the duty ratio of the DQS signal may experience a degradation in a period during which the DQS signal passes through, for example, a level converter, which performs a voltage level conversion from a voltage of an I/O power supply within the memory controller to a voltage of a Core power supply, or a signal transmission path.
In addition, since the timing margin for capturing the DQ signal is reduced due to the duty ratio degradation of the DQS signal, the reading timing may be out of the reduced timing margin in reading data by the memory interface. In this case, the memory interface may not accurately capture data and thus, a data abnormality may occur.
In particular, it is difficult to specify whether the data abnormality is caused by the duty ratio degradation because it is difficulty to observe the duty ratio degradation that has occurred within the memory interface.
The duty ratio degradation is not detected in a conventional technology in which the timing of the DQS signal is monitored to adjust a delay amount of the reception signal and thus, it is difficult to determine whether the data abnormality is caused by the duty ratio degradation.